View LZ21N3_1117779.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects that may occur in equipment using any sharp devices shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp device. 1 description the LZ21N3 is a 1/2-type (8.08 mm) solid-state image sensor that consists of pn photo-diodes and ccds (charge-coupled devices). with approximately 2 140 000 pixels (1 704 horizontal x 1 255 vertical), the sensor provides a stable high- resolution color image. features optical size : 8.08 mm (aspect ratio 4 : 3) interline scan format square pixel number of effective pixels : 1 650 (h) x 1 250 (v) number of optical black pixels e horizontal : 2 front and 52 rear e vertical : 3 front and 2 rear number of dummy bits e horizontal : 28 e vertical : 2 pixel pitch : 3.95 m (h) x 3.95 m (v) mg, g, cy, and ye complementary color mosaic filters supports monitoring mode low fixed-pattern noise and lag no burn-in and no image distortion blooming suppression structure built-in output amplifier built-in overflow drain voltage circuit and reset gate voltage circuit variable electronic shutter package : 20-pin half-pitch wdip [plastic] (wdip020-p-0500) row space : 12.20 mm pin connections precautions the exit pupil position of lens should be 30 to 50 mm from the top surface of the ccd. refer to "precautions for ccd area sensors" for details. LZ21N3 1/2-type interline color ccd area sensor with 2 140 k pixels LZ21N3 1od 2gnd 3ofd 4pw 5 rs 6nc 1 7nc 2 8 h1 9nc 3 10 h2 20 19 18 17 16 15 14 os gnd nc 5 nc 4 v1a v1b v2 13 v3a 12 v3b 11 v4 20-pin half-pitch wdip top view (wdip020-p-0500)
2 LZ21N3 pin description symbol pin name od output transistor drain os output signals rs reset transistor clock v1a , v1b , v2 , v3a , v3b , v4 vertical shift register clock h1 , h2 horizontal shift register clock pw p-well gnd ground nc 1 , nc 2 , nc 3 , nc 4 , nc 5 no connection overflow drain ofd absolute maximum ratings (t a = +25 ?c) parameter symbol rating unit output transistor drain voltage v od 0 to +15 v reset gate clock voltage v rs internal output v vertical shift register clock voltage v v v pw to +15 v horizontal shift register clock voltage v h e0.3 to +12 v voltage difference between p-well and vertical clock v pw -v v e24 to 0 v storage temperature t stg e40 to +85 ?c ambient operating temperature t opr e20 to +70 ?c 2 note notes : 1. do not connect to dc voltage directly. when ofd is connected to gnd, connect v od to gnd. overflow drain clock is applied below 22 vp-p. 2. do not connect to dc voltage directly. when rs is connected to gnd, connect v od to gnd. reset gate clock is applied below 8 vp-p. 3. when clock width is below 10 s, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be below 22 v. 1 v internal output v ofd overflow drain voltage 3 v 0 to +15 v v -v v voltage difference between vertical clocks
3 LZ21N3 recommended operating conditions parameter symbol min. typ. max. unit note ambient operating temperature t opr 25.0 ?c output transistor drain voltage v od 12.5 13.0 13.5 v notes : 1. use the circuit parameter indicated in "system configuration example" , and do not connect to dc voltage directly. 2. v pw is set below v vl that is low level of vertical shift register clock, or is used with the same power supply that is connected to v l of v driver ic. * to apply power, first connect gnd and then turn on v od . after turning on v od , turn on pw first and then turn on other powers and pulses. do not connect the device to or disconnect it from the plug socket while power is being applied. 1 v 20.9 19.5 18.6 v ofd overflow drain clock p-well voltage v pw e8.0 v vl v2 ground gnd 0.0 v v e6.65 e7.0 e7.35 v v1al , v v1bl , v v2l v v3al , v v3bl , v v4l vertical shift register clock low level intermediate level high level v v1ai , v v1bi , v v2i v v3ai , v v3bi , v v4i v v1ah , v v1bh v v3ah , v v3bh 12.5 0.0 13.0 13.5 v v low level horizontal shift register clock v h1l , v h2l e0.05 0.0 0.05 v high level v h1h , v h2h 4.5 4.8 5.5 v 1 v 5.5 4.8 4.5 v rs reset gate clock p-p level reset gate clock frequency f rs 17.94 mhz horizontal shift register clock frequency f h1 , f h2 17.94 mhz vertical shift register clock frequency f v1a , f v1b , f v2 f v3a , f v3b , f v4 7.87 khz p-p level
LZ21N3 4 characteristics (drive method : 1/30 s frame accumulation) (t a = +25 ?c, operating conditions : the typical values specified in " recommended operating conditions ". color temperature of light source : 3 200 k, ir cut-off filter (cm-500, 1 mmt) is used.) parameter symbol min. typ. max. unit note standard output voltage v o 150 mv 2 photo response non-uniformity prnu 10 % 3 saturation output voltage v sat 450 530 mv 4 dark output voltage v dark 0.5 3.0 mv 1, 6 dark signal non-uniformity dsnu 0.5 2.0 mv 1, 7 sensitivity r 140 180 mv 8 smear ratio smr e89 e82 db 9 image lag ai 1.0 % 10 blooming suppression ratio abl 1 000 11 output transistor drain current i od 4.0 8.0 ma notes : within the recommended operating conditions of v od , v ofd of the internal output satisfies with abl larger than 1 000 times exposure of the standard exposure conditions, and v sat larger than 320 mv. 1. t a = +60 ?c 2. the average output voltage under uniform illumination. the standard exposure conditions are defined as when vo is 150 mv. 3. the image area is divided into 10 x 10 segments under the standard exposure conditions. each segment's voltage is the average output voltage of all pixels within the segment. prnu is defined by (vmax e vmin)/vo, where vmax and vmin are the maximum and minimum values of each segment's voltage respectively. 4. the image area is divided into 10 x 10 segments. each segment's voltage is the average output voltage of all pixels within the segment. v sat is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. the operation of ofdc is high. (for still image capturing) 5. the image area is divided into 10 x 10 segments. each segment's voltage is the average output voltage of all pixels within the segment. v sat is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. the operation of ofdc is low. 6. the average output voltage under non-exposure conditions. 7. the image area is divided into 10 x 10 segments under non-exposure conditions. dsnu is defined by (vdmax e vdmin), where vdmax and vdmin are the maximum and minimum values of each segment's voltage respectively. 8. the average output voltage when a 1 000 lux light source with a 90% reflector is imaged by a lens of f4, f50 mm. 9. the sensor is exposed only in the central area of v/10 square with a lens at f4, where v is the vertical image size. smr is defined by the ratio of the output voltage detected during the vertical blanking period to the maximum output voltage in the v/10 square. 10. the sensor is exposed at the exposure level corresponding to the standard conditions. ai is defined by the ratio of the output voltage measured at the 1st field during the non-exposure period to the standard output voltage. 11. the sensor is exposed only in the central area of v/10 square, where v is the vertical image size. abl is defined by the ratio of the exposure at the standard conditions to the exposure at a point where blooming is observed. 5 mv 400 320
LZ21N3 5 pixel structure 1 650 (h) x 1 250 (v) 1 pin optical black (2 pixels) optical black (52 pixels) optical black (3 pixels) optical black (2 pixels) color filter array ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg ye g ye g ye g ye g ye g cy mg cy mg cy mg cy mg cy mg (1, 1 250) (1 650, 1 250) (1, 1) (1 650, 1) v3b v1b v3a v1b v3b v1b v3b v1a v3b v1b v3b v1b v3a v1b v3b v1b v3b v1a v3b v1b pin arrangement of the vertical readout clock
LZ21N3 6 timing chart notes : 1. do not use these signals immediately after field accumulation mode is transferred to frame accumulation mode for still image capturing. 2. do not use these signals immediately after frame accumulation mode is transferred to field accumulation mode for monitoring image. * apply at least an ofd shutter pulse to ofd in each field accumulation mode. os v3a v2 v1b v1a vd timing chart example ofdc ofd v4 v3b 263 525 1 1 263 525 656 1 263 525 1 656 1 656 1 (at ofd shutter operation) not for use (note 1) (number of vertical line) pulse diagram in more detail is shown in figures q to t after the next page. field accumulation mode frame accumulation mode at first frame accumulation mode field accumulation mode at first field accumulation mode qqwe rtqq ' q ' (1, 3, ... , 1247, 1249) frame accumulation mode (2, 4, ... , 1248, 1250) field accumulation mode (3, 8, 13, .. ) not for use (note 2) (3, 8, 13, .. ) field accumulation mode (3, 8, 13, .. ) (3, 8, 13, .. )
LZ21N3 7 v3a v2 v3b os v1b v1a hd vd ofd ofdc v4 q vertical transfer timing field accumulation mode 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 ob1 gmg yecy gmg yecy 818 313 gmg yecy gmg yecy 1238 1248 1233 1243 gmg yecy gmg yecy 1218 1228 1213 1223 yecy gmg yecy 1198 1208 1203 shutter speed 1/30 s v3a v2 v3b os v1b v1a hd vd ofd ofdc v4 519 520 521 522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ob1 gmg yecy gmg yecy 818 313 gmg yecy gmg yecy 1238 1248 1233 1243 gmg yecy gmg yecy 1218 1228 1213 1223 yecy gmg gmg yecy 1198 1208 1203 1193 q ' vertical transfer timing field accumulation mode shutter speed 1/30 s
LZ21N3 8 v3a v2 v3b os v1b v1a hd vd ofd ofdc v4 519 520 521 522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 gmg yecy gmg yecy 1238 1248 1233 1243 gmg yecy gmg yecy 1218 1228 1213 1223 yecy gmg gmg yecy 1198 1208 1203 1193 not for use w vertical transfer timing frame accumulation mode at first shutter speed 1/15 s ofd v3a ofdc v4 v3b v2 v1b v1a vd hd e vertical transfer timing frame accumulation mode 618 619 620 621 622 623 624 655 656 1 2 9 10 12 11 13 15 14 17 16 19 18 21 20 os ob2 1 3 5 gmg gmg gmg not for use charge swept transfer (1 368 stages) * do not use the frame signals immediately after accumulation mode is transferred to frame accumulation mode. * do not use the frame signals immediately after field accumulation mode is transferred to frame accumulation mode.
LZ21N3 9 ofd v3a ofdc v4 v3b v2 v1b v1a vd hd r vertical transfer timing frame accumulation mode 638 639 640 641 642 643 644 645 646 656 1 2 9 10 12 11 13 15 14 17 16 19 18 21 20 os ob1 ob3 2 4 yecy yecy gmg gmg gmg gmg gmg not for use charge swept transfer (684 stages) ob1 1249 1243 1247 1245 1241 ofd v3a ofdc v4 v3b v2 v1b v1a vd hd t vertical transfer timing field accumulation mode at first 640 641 642 643 644 656 6 57 1234 9 81012 11 13 15 14 17 16 19 18 21 20 os 1244 ob2 1246 1248 1250 yecy yecy yecy yecy shutter speed 1/15 s
LZ21N3 10 40.9 s (732 bits) 58.8 s (1 052 bits) (120 bits) (120 bits) 892 v3a v4 v3b v2 v1a hd 92 212 172 292 52 252 132 332 2280, 1 228 292 252 332 212 228 2280, 1 732 852 932 1172 1052 1012 972 6.7 s 6.7 s v1b readout timing field accumulation mode 40.9 s (732 bits) 58.8 s (1 052 bits) (120 bits) (120 bits) 892 972 v3a v3b v4 v2 v1a v1b e r 92 212 172 292 52 252 132 332 228 292 252 332 212 228 2280, 1 732 852 932 1012 6.7 s 6.7 s readout timing frame accumulation mode 892 1052 1172 92 212 172 292 52 252 132 332 228 932 1012 2280, 1 212 292 252 332 228 2280, 1 2280, 1 v3a v3b v4 v2 v1a v1b hd 972 * keep over 2.2 s when vertical transfer clock pulse is overlapping. * keep over 2.2 s when vertical transfer clock pulse is overlapping.
LZ21N3 11 os rs h2 h1 hd ob (52) horizontal transfer timing field accumulation mode-1 1 clk = 55.8 ns (= 1/17.9 mhz) 2280, 1 52 92 132 172 212 228 252 292 332 40 clk (= 2.2 s) double transfer ofd v4 v2 v1a v1b v3a v3b v4 v2 v1a v1b v3a v3b triple transfer 192 272 1111650
LZ21N3 12 os rs h2 h1 hd v4 v2 horizontal transfer timing field accumulation mode-2 1 clk = 55.8 ns (= 1/17.9 mhz) 332 v1a v1b v3a v3b 372 412 452 492 532 572 600 double transfer ofd v4 v2 v1a v1b v3a v3b triple transfer output (1 650) 1 1111111 ob (2) pre scan (28)
LZ21N3 13 os rs h2 h1 hd ob (52) horizontal transfer timing frame accumulation mode-1 1 clk = 55.8 ns (= 1/17.9 mhz) 2280, 1 .. 1650 52 92 132 172 212 228 252 292 332 40 clk (= 2.2 s) standard transfer ofd v4 v2 v1a v1b v3a v3b 192 272
LZ21N3 14 os rs h2 h1 hd horizontal transfer timing frame accumulation mode-2 1 clk = 55.8 ns (= 1/17.9 mhz) 332 372 412 452 492 532 572 600 standard transfer ofd v4 v2 v1a v1b v3a v3b output (1 650) 1 1111111 ob (2) pre scan (28)
LZ21N3 15 charge swept transfer timing e v1a v1b v4 v3a v3b v2 hd 621h 11h 12h 3h 2h 1h 656h 655h 623h 622h 13h 1 228 2242 2 42 162 122 82 2 42 162 122 82 12 3 4 1368 1367 1366 2262 22 62 142 102 2262 22 62 142 102 2242 v1a v1b v4 v3a v3b v2 hd charge swept transfer timing r 645h 11h 12h 3h 2h 1h 656h 655h 647h 646h 13h 1 228 2242 2 42 162 122 82 2 42 162 122 82 1234 684 683 682 2262 22 62 142 102 2262 22 62 142 102 2242 * keep over 1.1 s when vertical transfer clock pulse of charge swept transfer is overlapping. * keep over 1.1 s when vertical transfer clock pulse of charge swept transfer is overlapping.
LZ21N3 16 od pw ofd v2 v1b v3a v3b v4 gnd nc 1 nc 2 h1 nc 3 h2 os gnd nc 5 nc 4 v1a rs v 3b v 3a v 1b v 1a v ma v h v 4 v 2 v l v mb pofd nc v h h2 vh 1bx v 3x v 2x vh 3bx v 4x v 1x vh 3ax vh 1ax +v dd ofdx h1 rs v l (v pw ) ccd out v ofdh vh 3bx ofdx v 2x v 1x v 3x v dd gnd v 4x vh 3ax vh 1bx vh 1ax + + 1 2 3 4 5 6 7 8 12 24 23 22 21 20 19 18 17 13 11 14 10 15 9 16 2 3 4 5 6 7 8 19 18 1 20 17 16 15 14 13 9 10 12 11 lr36685 LZ21N3 (*1) (*1) v od ofdc 270 pf 1 m$ 1 m$ 5.6 k$ 47 k$ 0.01 f + 100 k$ 33 k$ 100 $ 0. 1 f 1.0 f + (*1) rs , ofd : use the circuit parameter indicated in this circuit example, and do not connect to dc voltage directly. system configuration example
packages for ccd and cmos devices 17 glass lid package 6.90 0.075 0.40 0.40 6.00 0.075 0.40 0.40 11.20 0.10 (2) 12.00 0.10 13.80 0.10 13.00 0.10 (2) 110 ccd 20 11 a center of effective imaging area and center of package rotation error of die : a = 1.0? max. ( 1 : effective imaging area) ( 2 : lid's size) 12.20 0.10 refractive index : nd = 1.5 0.50 0.05 (2) 1.41 0.05 0.25 0.10 12.20 0.04 0.02 0.02 (1) (1) a' a a a' 0.64 typ. 0.30 typ. p-1.27 typ. 0.20 m 3.50 0.10 2.40 0.10 2.90 0.10 ccd +0.30 e0 20 wdip (wdip020-p-0500) package (unit : mm)
precautions for ccd area sensors 1. package breakage in order to prevent the package from being broken, observe the following instructions : 1) the ccd is a precise optical component and the package material is ceramic or plastic. therefore, ? take care not to drop the device when mounting, handling, or transporting. ? avoid giving a shock to the package. especially when leads are fixed to the socket or the circuit board, small shock could break the package more easily than when the package isn?t fixed. 2) when applying force for mounting the device or any other purposes, fix the leads between a joint and a stand-off, so that no stress will be given to the jointed part of the lead. in addition, when applying force, do it at a point below the stand-off part. (in the case of ceramic packages) the leads of the package are fixed with low melting point glass, so stress added to a lead could cause a crack in the low melting point glass in the jointed part of the lead. (in the case of plastic packages) e the leads of the package are fixed with package body (plastic), so stress added to a lead could cause a crack in the package body (plastic) in the jointed part of the lead. 3) when mounting the package on the housing, be sure that the package is not bent. e if a bent package is forced into place between a hard plate or the like, the pack- age may be broken. 4) if any damage or breakage occurs on the sur- face of the glass cap, its characteristics could deteriorate. therefore, ? do not hit the glass cap. ? do not give a shock large enough to cause distortion. ? do not scrub or scratch the glass surface. even a soft cloth or applicator, if dry, could cause dust to scratch the glass. 2. electrostatic damage as compared with general mos-lsi, ccd has lower esd. therefore, take the following anti-static measures when handling the ccd : 1) always discharge static electricity by grounding the human body and the instrument to be used. to ground the human body, provide resistance of about 1 m$ between the human body and the ground to be on the safe side. 2) when directly handling the device with the fingers, hold the part without leads and do not touch any lead. glass cap package lead fixed stand-off fixed lead stand-off low melting point glass 18 precautions for ccd area sensors
3) to avoid generating static electricity, a. do not scrub the glass surface with cloth or plastic. b. do not attach any tape or labels. c. do not clean the glass surface with dust- cleaning tape. 4) when storing or transporting the device, put it in a container of conductive material. 3. dust and contamination dust or contamination on the glass surface could deteriorate the output characteristics or cause a scar. in order to minimize dust or contamination on the glass surface, take the following precautions : 1) handle the ccd in a clean environment such as a cleaned booth. (the cleanliness level should be, if possible, class 1 000 at least.) 2) do not touch the glass surface with the fingers. if dust or contamination gets on the glass surface, the following cleaning method is recommended : ? dust from static electricity should be blown off with an ionized air blower. for anti- electrostatic measures, however, ground all the leads on the device before blowing off the dust. ? the contamination on the glass surface should be wiped off with a clean applicator soaked in isopropyl alcohol. wipe slowly and gently in one direction only. frequently replace the applicator and do not use the same applicator to clean more than one device. note : in most cases, dust and contamination are unavoidable, even before the device is first used. it is, therefore, recommended that the above procedures should be taken to wipe out dust and contamination before using the device. 4. other 1) soldering should be manually performed within 5 seconds at 350 ?c maximum at soldering iron. 2) avoid using or storing the ccd at high tem- perature or high humidity as it is a precise optical component. do not give a mechanical shock to the ccd. 3) do not expose the device to strong light. for the color device, long exposure to strong light will fade the color of the color filters. 19 precautions for ccd area sensors

▲Up To Search▲

Price & Availability of LZ21N3

	To Download LZ21N3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .